1. Field of the Invention
This invention relates to a MOS type semiconductor integrated circuit apparatus having a well bias voltage supply circuit, and in particular to an apparatus of this type having a plurality of well bias voltage supply circuits for supplying different well bias voltages.
2. Description of the Related Art
In general, a MOS type semiconductor integrated circuit apparatus has a well region formed therein and is provided with various elements such as a MOS transistor. A well bias voltage of a predetermined value is supplied to the well region so as to stabilize the threshold voltage of the MOS transistor formed therein.
In the MOS type semiconductor integrated circuit apparatus, however, if the well potential of part of a circuit incorporated in the apparatus is incidentally changed during operation thereof, the change may adversely affect the overall circuit, causing the circuit to be unstable. This will hereinbelow be explained in detail.
FIG. 11 shows the waveform of an output generated from an output circuit incorporated in the MOS type semiconductor integrated circuit apparatus. As shown in the figure, where an output data D is changed from "H" level to "L" level, undershoot is caused in the output potential Vout. V.sub.BB denotes a well bias voltage, which is set to -2.0V. The well bias voltage slightly fluctuates as indicated by A where undershoot is caused in the output voltage Vout, which adversely affects operation of an element such as a memory device.
FIG. 8 is a cross sectional view, showing the elements of an output transistor incorporated in the output circuit. In FIG. 8, reference numeral 81 denotes an n-type semiconductor substrate, reference numeral 82 denotes a p-type well region, reference numerals 83 and 84 denote an n-type diffusion region for forming the drain and source regions of the output transistor, and reference numeral 85 denotes a gate electrode. If the output voltage Vout (the drain potential of the output transistor) becomes lower than the well potential, a pn junction consisting of an n-type diffusion region 83 as the drain region and a p-type well region 82 is forwardly biased. Thus, current flows toward the n-type diffusion region 83 and p-type well region 82, causing a change in well potential.
In the above integrated circuit apparatus, the well regions of circuits are electrically connected to one another, so that a change in the well potential of an input/output circuit adversely affects the well potential of each of circuits other than the input/output circuit, causing circuit operation to be unstable. Therefore, a malfunction may occur in a logic circuit, and data in the logic circuit may disappear in a memory circuit. In particular, operation of a SRAM (Static Random Access Memory) circuit incorporating an E/R type memory cell consisting of a high resistance serving as load element is more liable to become unstable since it is inherently difficult to keep the circuit stable.
Moreover, in a MOS type semiconductor integrated circuit apparatus having a logic circuit and a memory circuit, the logic circuit must incorporate a MOS transistor of a low threshold voltage so as to achieve high speed operation, and the memory circuit must incorporate a MOS transistor of a high threshold voltage so as to stabilize the operation of the circuit. Actually, however, the well potential of the logic circuit cannot be set independent of that of the memory circuit, that is, one of the circuits cannot have an appropriate threshold voltage.